Console
A 94 MHz R4300 beside the Reality Coprocessor, with 4 MiB of RDRAM shared between processor, geometry engine and rasterizer rather than split into system and video memory.
A Nintendo 64 with the three-handled controller.
The Nintendo 64 differs from the PlayStation in two architectural respects. Its memory is unified: one RDRAM pool is used in parallel by the CPU, the RSP microcode engine, the RDP graphics pipeline and the I/O interfaces. The PlayStation keeps 2 MiB of main memory and 1 MiB of video memory in separate pools connected only by DMA. Its geometry stage is also programmable. The RSP runs microcode, so software rather than fixed silicon determines what the machine does with a triangle.
Those choices make the capacity figures harder to compare than they look. Four megabytes shared between everything is not four megabytes of system memory, and the machine that has to hold textures in the same pool as game state makes a different trade from one with a dedicated frame buffer.
| Component | Role | Count | Clock | Capacity |
|---|---|---|---|---|
| MIPS R4300 (Nintendo 64 CPU) The programming manual states a round 94 MHz. | Main CPU | 1 | 94 MHz Nominal clock | — |
| Reality Coprocessor (RCP) Provisional; see the measurement record for why this figure is not yet accepted. | GPU | 1 | 62.6 MHz Nominal clock | — |
| Nintendo 64 main memory (RDRAM) Used in parallel by the CPU, the RSP, the RDP and the I/O interfaces. | Unified memory | 1 | — | 4 MiB shared |
provisional A figure marked provisional is recorded but not accepted: its evidence is unsettled. It may rely on one source, an unconfirmed announcement, or a digit read from a damaged scan. The reason appears under the figure. The catalog shows the figure but never uses it in a multiplier. How records are judged.
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Clock frequency cpu | 94 MHz | Confirmed | Vendor-rated | Nominal clock Stated by the vendor R4300 CPU, from the manual's clock speeds and bus bandwidth list. The manual states a round 94 MHz, so this figure carries two significant digits and nothing more. Other accounts of this console quote a more precise rate; none is cited here, and adopting one would be publishing a number this project has not sourced. | |
| Clock frequency gpu provisional | 62.6 MHz | Confirmed | Vendor-rated | Nominal clock Stated by the vendor Reality Coprocessor, from the manual's clock speeds and bus bandwidth list. Held provisional rather than approved. The digits are legible, but the same list renders 110 as "liO" and the surrounding prose is badly corrupted, so a third digit read off this scan is not something to publish as fact. A provisional figure is visible but never feeds an automatic multiplier; it needs a second source before it can be accepted. | |
| Memory capacity whole-system | 4 MiB | Confirmed | Derived | Design capacity Computed here from figures the vendor stated One pool shared by the processor, the coprocessor and the I/O interfaces, so the machine’s memory is a single figure. Adds 1 memory-capacity figure obtained by design-capacity. Nothing in the catalog is left out of it. A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records. | |
| Memory bandwidth whole-system provisional | 500 MB/s | Confirmed | Derived | Theoretical peak Computed here from figures the vendor stated One pool for everything: the manual states that the processor, the signal processor, the drawing processor and the I/O interfaces use this memory in parallel. Adds 1 memory-bandwidth figure obtained by theoretical-peak. Nothing in the catalog is left out of it. A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records. |
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Peak FP32 rate gpu | unknown The programming manual describes the Reality Coprocessor by what its microcode does and never rates it in floating-point operations per second. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor Unknown rather than not-applicable: the R4300 has a floating-point unit and the signal processor is a vector machine, so the quantity exists. Nintendo simply never published a rate for it. The console generation that started quoting floating-point figures is the next one. | |
| Rated power consumption whole-system | unknown The programming manual is written for developers and rates no power for the console. | Not stated | Vendor-rated | Rated power Stated by the vendor Recorded as asked and unanswered. A figure is printed on the console’s own supply, but a nameplate photograph is not a source this catalog accepts, and Nintendo’s developer documentation does not repeat it. |
provisional A figure marked provisional is recorded but not accepted: its evidence is unsettled. It may rely on one source, an unconfirmed announcement, or a digit read from a damaged scan. The reason appears under the figure. The catalog shows the figure but never uses it in a multiplier. How records are judged.
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Memory capacity memory | 4 MiB | Confirmed | Vendor-rated | Design capacity Stated by the vendor Main memory of the retail console, built from 9 bit RDRAMs. One pool shared by the CPU, the RSP, the RDP and the I/O interfaces. It is not comparable like for like with the PlayStation's 2 MiB of main memory, because that machine has a further 1 MiB of video memory the CPU cannot reach and this one does not separate the two. | |
| Memory bandwidth memory provisional | 500 MB/s | Confirmed | Theoretical | Theoretical peak Stated by the vendor The single RDRAM pool, which the manual states is used in parallel by the processor, the signal processor, the drawing processor and the I/O interfaces. Provisional, like the graphics clock on the same page and for the same reason: the bullet this is read from is the one whose own clock figure the scan destroys, so a legible number on an illegible line waits for a second source. Note also what the manual counts: "9 bit bytes at 500 M/sec". The ninth bit is not the programmer’s, so this is 500 million bytes per second of data on a bus carrying rather more than that. |
4 194 304 B
a + b + … sum v1 Adds 1 memory-capacity figure obtained by design-capacity. Nothing in the catalog is left out of it. A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records.
500 000 000 B/s
a + b + … sum v1 Adds 1 memory-bandwidth figure obtained by theoretical-peak. Nothing in the catalog is left out of it. A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records.
The release date is editorial context; the cited manual is an October 1996 draft and does not date the launch. The scan of that manual is badly degraded, so no RDRAM clock or bandwidth figure is recorded: the clock-speed list gives an RDRAM entry that can only be reconstructed from the letterforms, and a figure that has to be guessed at is not published. The Expansion Pak that doubles main memory to 8 MiB is not recorded either, for want of a citation in this document.