Processor
Emotion Engine
Sony and Toshiba's 128 bit CPU for the PlayStation 2: a superscalar MIPS core with 16 kB of instruction cache, 8 kB of data cache and 16 kB of scratchpad, flanked by two vector units carrying nine floating-point multiply-add units between them.
- Manufacturer
- Sony Computer Entertainment / Toshiba
- Architecture
- MIPS III with 128-bit multimedia extensions and two vector units
- Introduced
- March 1999
- Width
- 128 bit
- Word size
- 64 bit
- Capacity
- 16 kB
- Capacity
- 8 kB
- Core count
- 1
- Instruction set
- MIPS III (partly MIPS IV) plus a 128-bit parallel multimedia instruction set
- Record status
- approved
Figures
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Peak FP32 rate cpu | 6.2 GFLOP/s | Confirmed | Vendor-rated | Theoretical peak Stated by the vendor Whole chip: the FPU coprocessor together with vector units VU0 and VU1, which hold nine floating-point multiply-add units and three dividers between them. Sony states the rate without an operation mix, a precision or a benchmark, so it is a vendor peak rather than an achieved result. It is not comparable with the Dreamcast's floating-point figure, which Sega derived from a specific matrix-multiplication workload. |
Fitted to
Editorial notes
"128-bit" describes the register and bus width used by the multimedia instructions, not the address or integer word size, which are 64 bit. The floating-point capacity Sony quotes belongs to the whole chip — the FPU coprocessor plus the two vector units — rather than to the core alone, which is why the peak FP32 figure is recorded against the component and not against any one of its blocks.