Processor
MIPS R10000
A four-way superscalar, out-of-order 64 bit processor with an on-die floating-point unit. It is the first machine in this catalog where asking for a floating-point rate makes sense at all.
- Manufacturer
- MIPS Technologies
- Architecture
- MIPS IV
- Introduced
- 1996
- Word size
- 64 bit
- Capacity
- 32 kB
- Capacity
- 1 MB
- Frequency
- 250 MHz
- Core count
- 1
- Thread count
- 1
- Instruction set
- MIPS IV
- Record status
- approved
Figures
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Peak FP32 rate cpu | 500 MFLOP/s | Confirmed | Derived | Theoretical peak Computed here from figures the vendor stated One R10000 at 250 MHz, both floating-point units issuing on every cycle. Computed here, not published anywhere. Nobody rated this processor in floating-point operations per second: a processor of 1996 was documented by what its units retire per cycle, and the manual says the adder and the multiplier each accept one operation every cycle and stops there. The multiplication is the derived claim this record names, with both constants cited to that manual. It is an upper bound twice over — every unit fed on every cycle, nothing stalling — and the same figure holds at double precision, because the manual gives the multiplier one repeat rate for both. |
Fitted to
Editorial notes
The SPEC result files list the floating-point unit separately as a "MIPS R10010 Floating Point Chip", which is how SGI reported the on-die FPU revision. Caches in the Octane configurations recorded here are 32 kB instruction plus 32 kB data on chip, with 1 MB of unified secondary cache.