Guidance computer
The computer that flew Apollo. A 31.7 kg, 70 W machine with 2048 words of erasable memory and 36 864 words of woven read-only rope, carried by both the command module and the lunar module.
The Apollo Guidance Computer's main case, with the display and keyboard unit — the DSKY — through which the crew worked it.
Block II is the flight configuration of the Apollo Guidance Computer, developed from Block I after the experience of the early program showed that both fixed and erasable memory had to grow. The rope memory went from 24 576 to 36 864 words and the erasable memory doubled to 2048; the order code grew from 11 normal instructions to 34. A change from high-power to low-power micrologic cut power consumption from 100 W to 70 W and weight from 39.4 kg to 31.7 kg while adding roughly a third more logic gates. The memory-cycle time stayed at 11.7 µs, but multiplication became 2.5 times faster. Both memories are addressable by any instruction: there is no hierarchical distinction between them beyond the inability of a program to change the fixed part.
| Component | Role | Count | Clock | Capacity |
|---|---|---|---|---|
| Apollo Guidance Computer Block II processor Master oscillator; the 1.024 MHz spacecraft reference is derived from it by a single divide-by-two stage. | Main CPU | 1 | 2.048 MHz Nominal clock | — |
| Apollo Guidance Computer core rope memory Six rope modules of 6144 words each. The capacity given is the total across all six. | System memory | 6 | — | 36 864 words |
| Apollo Guidance Computer erasable core memory The first eight locations are central and special registers rather than general storage. | System memory | 1 | — | 2048 words |
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Memory capacity (words) whole-system | 2048 words | Confirmed | Derived | Design capacity Computed here from figures the vendor stated The erasable core memory. The 36 864 words of fixed rope memory are excluded and named on the claim. Adds 1 memory-capacity-words figure obtained by design-capacity. Left out: 36 864 words of fixed rope memory (woven at manufacture and unwritable in flight, so it is storage the machine reads from rather than memory it works in). A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records. | |
| Rated power consumption whole-system | 70 W | Confirmed | Vendor-rated | Rated power Stated by the vendor Complete computer including memory, power supply and packaging. Block I drew 100 W. A design figure for the whole unit, not a measured draw under a stated workload and not a cooling-design target. It is not comparable with a component TDP in either direction. |
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Memory bandwidth memory | unknown The report describes the memory by cycle time and word length rather than by a transfer rate, which is how core-memory machines were specified. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor Unknown, and the absence says something about the era rather than about the document. A machine whose timing is quoted as an 11.7 microsecond memory cycle is being described in the unit that mattered; bytes per second is a later question, and multiplying the cycle time by the word length to answer it would be this project’s arithmetic rather than the report’s. | |
| Whole-system power draw whole-system | unknown No measured draw under a stated workload has been found in an acceptable source. The 70 W design rating is recorded separately and is a different quantity. | Not stated | Measured | Wall measurement Stated by the vendor |
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Clock frequency cpu | 2.048 MHz | Confirmed | Vendor-rated | Nominal clock Stated by the vendor Master oscillator rate, stated by the report as 2.048 megapulses per second. | |
| Memory cycle time cpu | 11.7 µs | Confirmed | Vendor-rated | Nominal cycle time Stated by the vendor Twelve time pulses of 0.977 µs. Fixed and erasable memory share one cycle time. The report gives 11.7 µs both in table I and in the running text. Twelve pulses of 0.977 µs would be 11.724 µs; the rounded figure the report states is the one recorded. | |
| Instruction execution time cpu | 23.4 µs | Confirmed | Vendor-rated | Addition instruction Stated by the vendor Single-precision addition: two 11.7 µs memory cycles. | |
| Instruction execution time cpu | 46.8 µs | Confirmed | Vendor-rated | Multiplication instruction Stated by the vendor Four 11.7 µs memory cycles. Block I took 117 µs for the same operation. Not comparable with the addition time: a different instruction is a different comparability group, and the ratio between them describes this machine's order code rather than its speed. |
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Peak FP32 rate cpu | not applicable The AGC has no floating-point hardware. Its arithmetic unit is a one's-complement fixed-point adder with shifting gates, so there is no rate to state — the question does not apply. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor | |
| Peak FP64 rate cpu | not applicable No floating-point hardware. The double-precision instructions in the Block II order code operate on pairs of 15 bit fixed-point words, which is not double-precision floating point. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor |
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Memory capacity (words) memory | 36 864 words | Confirmed | Vendor-rated | Design capacity Stated by the vendor Six rope modules; total fixed read-only capacity of the Block II computer. A word is 15 bit plus parity. Converting this capacity to bytes needs the word width and is published as a derived claim, never as a unit conversion. |
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Memory capacity (words) memory | 2048 words | Confirmed | Vendor-rated | Design capacity Stated by the vendor Coincident-current ferrite core array wired in 32 by 64 planes. The first eight locations are central and special registers rather than general storage. |
18×
a ÷ b ratio v1 Compares memory-capacity-words at memory scope, obtained by design-capacity. Valid only within this comparability group, and reported to 4 significant digits — the precision of the least precise input.
2048 words
a + b + … sum v1 Adds 1 memory-capacity-words figure obtained by design-capacity. Left out: 36 864 words (woven at manufacture and unwritable in flight, so it is storage the machine reads from rather than memory it works in). A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records.
3.5×
a ÷ b ratio v1 Compares instruction-execution-time at cpu scope, obtained by add-instruction. Valid only within this comparability group, and reported to 2 significant digits — the precision of the least precise input.
Recorded as a system in its own right rather than as a component, because it is a complete computer with its own power, packaging and display keyboard, and because its published weight and power figures describe the whole unit. The release date is editorial context for when the Block II configuration entered the program; it is not a figure carried by the cited report, which traces the Block I to Block II change without dating it. Every measurement attached to this system comes from the report.