Processor
Apollo Guidance Computer Block II processor
A one's-complement fixed-point processor built entirely from a single type of integrated-circuit NOR gate. Its 15 bit word carries a sixteenth parity bit, and every instruction lasts a whole number of 11.7 µs memory cycles.
- Manufacturer
- MIT Instrumentation Laboratory / Raytheon
- Architecture
- AGC Block II
- Introduced
- 1966
- Word size
- 15 bit
- Frequency
- 1.024 MHz
- Core count
- 1
- Contextual value
- 0.977 µs
- Contextual value
- 11.724 µs
- Contextual value
- 117 µs
- Instruction set
- AGC Block II
- Record status
- approved
Figures
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Clock frequency cpu | 2.048 MHz | Confirmed | Vendor-rated | Nominal clock Stated by the vendorMaster oscillator rate, stated by the report as 2.048 megapulses per second. | |
| Memory cycle time cpu | 11.7 µs | Confirmed | Vendor-rated | Nominal cycle time Stated by the vendorTwelve time pulses of 0.977 µs. Fixed and erasable memory share one cycle time. The report gives 11.7 µs both in table I and in the running text. Twelve pulses of 0.977 µs would be 11.724 µs; the rounded figure the report states is the one recorded. | |
| Instruction execution time cpu | 23.4 µs | Confirmed | Vendor-rated | Addition instruction Stated by the vendorSingle-precision addition: two 11.7 µs memory cycles. | |
| Instruction execution time cpu | 46.8 µs | Confirmed | Vendor-rated | Multiplication instruction Stated by the vendorFour 11.7 µs memory cycles. Block I took 117 µs for the same operation. Not comparable with the addition time: a different instruction is a different comparability group, and the ratio between them describes this machine's order code rather than its speed. |
2 documented absences
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Peak FP32 rate cpu | not applicable The AGC has no floating-point hardware. Its arithmetic unit is a one's-complement fixed-point adder with shifting gates, so there is no rate to state — the question does not apply. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor | |
| Peak FP64 rate cpu | not applicable No floating-point hardware. The double-precision instructions in the Block II order code operate on pairs of 15 bit fixed-point words, which is not double-precision floating point. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor |
Fitted to
Editorial notes
The Block II order code has 34 normal instructions against Block I's 11, and multiplication is 2.5 times faster than Block I at the same memory-cycle time. There is no floating-point hardware: the arithmetic unit is an adder with shifting gates.