Processor
MOS Technology 6510
A 6502 with an on-chip eight-bit bidirectional I/O port. Internally identical to the 6502 for software compatibility; the extra port is what lets the Commodore 64 bank ROM and I/O in and out of a 16 bit address space.
- Manufacturer
- MOS Technology
- Architecture
- MOS 6502
- Introduced
- 1982
- Width
- 16 bit
- Word size
- 8 bit
- Frequency
- 1 MHz
- Frequency
- 2 MHz
- Core count
- 1
- Instruction set
- MOS 6502
- Record status
- approved
Figures
2 documented absences
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Native instruction rate cpu | unknown No acceptable source states one, and there is no single correct answer to state: 6502 instructions take between two and seven cycles depending on the instruction and its addressing mode, so an instruction rate exists only for a specific mix of instructions. Dividing the clock by one cycle per instruction — the usual shortcut to "about 1 MIPS" — describes no real workload. | Not stated | Measured | Instruction mix Stated by the vendor | |
| Peak FP32 rate cpu | not applicable No floating-point hardware. The 6510 does decimal and binary integer arithmetic in an eight-bit accumulator; the Commodore 64's floating point is a software library in the BASIC ROM, which is not a property of the processor. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor |
Fitted to
Editorial notes
56 instructions, thirteen addressing modes, decimal and binary arithmetic, an eight-bit data bus and a sixteen-bit address bus. The part is rated for 1 MHz and 2 MHz operation, which is a speed grade rather than the rate any particular machine clocks it at.