About this machine

The quoted processor and graphics frequencies are published ceilings of variable ranges, so they use peak-clock rather than pretending that either is a fixed nominal rate.

Configuration

Retail hardware

Component Role Count Clock Capacity
AMD Zen 2 Main CPU 1 3.5 GHz Peak clock
AMD RDNA 2 graphics GPU 1 1.6 GHz Peak clock
Valve Steam Deck unified memory Unified memory 1 16 GiB shared

Figures for the whole machine

Valve Steam Deck: system figures
Metric Value Evidence Basis Method Source
Clock frequency cpu 3.5 GHz Confirmed Vendor-rated Peak clock Stated by the vendor Zen 2, 4 cores and 8 threads, at the top of its published range. The published ceiling of a range Valve states as 2.4 GHz–3.5 GHz, not a rate the processor holds. The same line gives the processor's own floating-point capability as up to 448 GFlops, which is a different part from the graphics rate this catalog records.
Clock frequency gpu 1.6 GHz Confirmed Vendor-rated Peak clock Stated by the vendor LCD model, 8 RDNA 2 compute units. Valve states this frequency beside the compute-unit count and the floating-point rate derived from both, so it is the ceiling the 1.6 TFLOP/s figure assumes rather than an independent claim.
Peak FP32 rate gpu 1.6 TFLOP/s Confirmed Vendor-rated Theoretical peak Stated by the vendor LCD model, 8 RDNA 2 compute units at up to 1.6 GHz. One of the few consumer machines whose maker states a floating-point rate and its precision together. It is the GPU's rate; Valve gives the CPU's FP32 capability separately as up to 448 GFlops.
Memory bandwidth memory 88 GB/s Confirmed Derived Theoretical peak Computed here from figures the vendor stated LPDDR5 at its rated transfer rate across the full interface. Valve publishes the transfer rate and the channel geometry and no bandwidth, so this is the arithmetic between them rather than a figure anybody stated. It is the bus at its peak, shared between the processor and the graphics units on the same chip, so no single part of the machine ever sees all of it.
Memory transfer rate memory 5500 MT/s Confirmed Vendor-rated Nominal transfer rate Stated by the vendor 16 GB of on-board LPDDR5 as fitted to the LCD model. A speed grade rather than a measurement, so it is exact as written. The OLED model's page states 6400 MT/s, which is why that page cannot be read onto this machine.
Memory bus width memory 128 bit Confirmed Vendor-rated Design capacity Stated by the vendor Valve states the interface as quad 32 bit channels. The width recorded here is those four channels stated together, which is the same fact in the unit this metric uses rather than an inference about the hardware.
Memory capacity whole-system 17 179 869 184 B Confirmed Derived Design capacity Computed here from figures the vendor stated Adds 1 memory-capacity figure obtained by design-capacity. Nothing in the catalog is left out of it. A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records.
Rated power consumption whole-system 45 W Confirmed Vendor-rated Rated power Stated by the vendor Bundled USB Type-C PD3.0 power supply. A supply rating stated in watts by Valve, not a measured draw. The APU's own 4 W–15 W operating window is a different quantity for a different part and is not recorded here.

Figures for its components

Valve Steam Deck unified memory
Metric Value Evidence Basis Method Source
Memory capacity memory 16 GiB Confirmed Vendor-rated Design capacity Stated by the vendor On-board LPDDR5 as fitted to the LCD model. Valve writes "16 GB" of a memory part, which is the binary quantity in the way memory has always been sold; it is recorded as such rather than converted to the decimal prefix the letters would otherwise mean.

Derived figures and comparisons

Computed by this project rather than read from a source, and recomputed from their inputs on every build.

88 000 000 000 B/s

Formula
transfer rate × bus width ÷ 8 bits per byte memory-bandwidth-from-transfer-rate v1
Inputs
  • valve-steam-deck Memory transfer rate: 5500 MT/s
  • valve-steam-deck Memory bus width: 128 bit
Rounding
half-up , 2 significant digits

Multiplies a published transfer rate by the recorded interface width and divides by the recorded bits-per-byte constant. That is how a memory specification is read when the maker states the rate and the width but no bandwidth. It is the bus at its peak: refresh, bus turnaround and contention between the parts sharing the memory all take some of it back, and no workload sees the whole figure. Reported to 2 significant digits — the precision of the transfer rate, since the width is exact.

17 179 869 184 B

Formula
a + b + … sum v1
Inputs
  • valve-steam-deck-ram Memory capacity: 16 GiB
Rounding
none , 11 significant digits

Adds 1 memory-capacity figure obtained by design-capacity. Nothing in the catalog is left out of it. A total is only as trustworthy as the decision about what belongs in it, so both the terms and the exclusions are named records.

Sources

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