Processor
Saturn Launch Vehicle Digital Computer
A stored-program, general-purpose, serial, fixed-point binary computer built from triple-redundant logic, with ultrasonic glass delay lines standing in for arithmetic registers. It flew the Saturn launch vehicle from lift-off to orbit.
- Manufacturer
- IBM Federal Systems Division
- Architecture
- LVDC
- Introduced
- 1966
- Width
- 24 bit
- Word size
- 26 bit
- Width
- 28 bit
- Core count
- 1
- Contextual value
- 23.4 µs
- Instruction set
- LVDC
- Record status
- approved
Figures
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Clock frequency cpu | 2.048 MHz | Confirmed | Vendor-rated | Nominal clock Stated by the vendorFour clocks per bit, giving 512 kilobits per second in serial operation. The same clock rate as the Apollo Guidance Computer, and the coincidence says nothing about their speed: the LVDC is a serial machine that spends four clocks per bit, so it adds in 82 µs against the AGC's 23.4 µs. | |
| Instruction execution time cpu | 82 µs | Confirmed | Vendor-rated | Addition instruction Stated by the vendorAdd-subtract, 26 bit accuracy. Add-subtract and multiply-divide run simultaneously. | |
| Instruction execution time cpu | 656 µs | Confirmed | Vendor-rated | Division instruction Stated by the vendor24 bit accuracy. | |
| Instruction execution time cpu | 328 µs | Confirmed | Vendor-rated | Multiplication instruction Stated by the vendor24 bit accuracy. |
2 documented absences
| Metric | Value | Evidence | Basis | Method | Source |
|---|---|---|---|---|---|
| Peak FP32 rate cpu | not applicable The LVDC is a fixed-point machine, as its own characteristics table states in the type row. There is no floating-point rate to give. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor | |
| Peak FP64 rate cpu | not applicable Fixed-point machine. The 26 bit data word carries 25 magnitude bits and a sign bit, not an exponent. | Not stated | Vendor-rated | Theoretical peak Stated by the vendor |
Fitted to
Editorial notes
The 26 bit data word is 25 magnitude bits plus a sign bit; two further parity bits bring the 28 bit memory word. Two instructions fit in one memory word. Being serial, it clocks four times per bit, giving 512 kilobits per second from a 2.048 MHz clock. Triple modular redundancy divides each of three identical logic channels into seven voted modules.